#ifndef AFE_DATA_APPLICATION_H_
#define AFE_DATA_APPLICATION_H_
// 
// Default values
//

//#define DEFAULT_AFE_REG_GPIO1IN				0x00
																		/*!< GPIO1IN b7:b0
																		       G1p0IN		 (b7) = 0
																			   G1p1IN		 (b6) = 0
																			   G1p2IN		 (b5) = 0
																			   G1p3IN		 (b4) = 0
																			   G1p5IN		 (b3) = 0
																			   G1p6IN		 (b2) = 0
																			   G1p7IN		 (b1) = 0
																			   G1p8IN        (b0) = 0 */
																			   																			   	
//#define DEFAULT_AFE_REG_GPIO1OUT			0x60
																		/*!< GPIO1IN b7:b0
																		       PU12p5k		 (b7) = 0
																			   GAIN[1]		 (b6) = 1
																			   GAIN[0]		 (b5) = 1
																			   TRK HSPWM	 (b4) = 0
																			   G1p5OUT		 (b3) = 0
																			   G1p6OUT		 (b2) = 0
																			   G1p7OUT		 (b1) = 0
																			   G1p8OUT       (b0) = 0 */

//#define DEFAULT_AFE_REG_GPIO1GP			0x89						/*!< GPIO1GP b7:b0
#define DEFAULT_AFE_REG_GPIO1GP				0x81						/*!< GPIO2GP b7:b0
																		       DCDeglitch     (b7) = 1
																		       REG5V90		  (b6) = 0
																		       G1p4OUT        (b5) = 0
																		       G1p4RD         (b4) = 0 or 1 for Ext. HW OC
																		       G1p4WR		  (b3) = 0
																		       GG2RD          (b2) = 0
																		       G1p7RD		  (b1) = 0
																		       G1p8RD         (b0) = 1 */
//#define DEFAULT_AFE_REG_GPIO2GP           0x43    					/*!< GPIO2GP b7:b0
#define DEFAULT_AFE_REG_GPIO2GP            	0xC3    					/*!< GPIO2GP b7:b0
																		       OCfromGPIO     (b7) = 0    1 for  EXT GPIO
																		       PreDrv HLD     (b6) = 1    [Do not Clear pre-driver restart over OC]
																		       G1p11OUT       (b5) = 0 
																		       G1p11RD        (b4) = 0 
																		       G1p11WR        (b3) = 0 
																		       GG2WR          (b2) = 0
																		       G1p7WR         (b1) = 1
																		       G1p8WR         (b0) = 1 */
#define DEFAULT_AFE_REG_GPIO3GP				0x00						/*!< GPIO3GP b7:b0
																		       G1p9IN	      (b7) = 0    
																		       G1p10IN        (b6) = 0 
																		       G1p9RD         (b5) = 0 
																		       G1p9WR         (b4) = 0 
																		       G1p9OUT        (b3) = 0 
																		       G1p10OUT       (b2) = 0
																		       G1p10RD        (b1) = 0
																		       G1p10WR        (b0) = 0 */
         																		    
#define DEFAULT_AFE_REG_DAC1				0x0D						/*!< DAC1 b7:b0: 
                                                                               Major 1        (b7) = 0
                                                                               Major 0        (b6) = 0
                                                                               Minor 1        (b5) = 0
                                                                               Minor 0        (b4) = 0
                                                                               AMUX SEL 1     (b3) = 1     Use DAC output for OC (AMuxSel = 11b)
                                                                               AMUX SEL 0     (b2) = 1
                                                                               DAC9           (b1) = 0
                                                                               DAC8           (b0) = 1 */
//#define DEFAULT_AFE_REG_DAC2				0x66    					/*< DAC2 b7:b0                                                                               
#define DEFAULT_AFE_REG_DAC2				0x99    					/*< DAC2 b7:b0
                                                                               DAC7:DAC0      (b7:b0) = 0x99    DAC = 0x199 - 40% fullscale */
#define DEFAULT_AFE_REG_ADC1				0x00						/*!< ADC1 b7:b0: 
                                                                               ADCSEL3        (b7) = 0
                                                                               ADCSEL2        (b6) = 0
                                                                               ADCSEL1        (b5) = 0
                                                                               ADCSEL0        (b4) = 0
                                                                               ISNSHiGain     (b3) = 0     
                                                                               ADC START      (b2) = 0
                                                                               ADC9           (b1) = 0
                                                                               ADC8           (b0) = 0 */
#define DEFAULT_AFE_REG_ADC2				0x00						/*< ADC2 b7:b0
                                                                               ADC7:ADC0      (b7:b0) = 0x00   */
//#define DEFAULT_AFE_REG_ICOMP				0xD0						 /*!< Icomp/PreDrv b7:b0
#define DEFAULT_AFE_REG_ICOMP				0xD1						 /*!< Icomp/PreDrv b7:b0
                                                                               PreDrv EN      (b7) = 1     Pre-drivers enabled
                                                                               HYS DCDC1      (b6) = 1     DC-DC hysteresis = 01b
                                                                               HYS DCDC0      (b5) = 0    
                                                                               HSD PWM        (b4) = 1     HS drivers get signal from controller
                                                                               ADC Fast SPI   (b3) = 0     Serial port operates normally
                                                                               ADC TRK        (b2) = 0     Returns to standby mode between conversions
                                                                               IcompHys1      (b1) = 0     20 mV
                                                                               IcompHys0      (b0) = 1 */
                                                                               
#define DEFAULT_AFE_REG_HALLSNS				0x40						/*!< Hall Sns / Phase Cmp b7:b0
                                                                               Auto ADC       (b7) = 0    Does not automatically sample ADC at falling edge of PWM
                                                                               ADC 25MHz      (b6) = 1    ADC uses 25MHz sampling clock
                                                                               SelCmp SH      (b5) = 0    Enables filtering on comparator output signals
                                                                               PHC Hys En     (b4) = 0    Enable hysteresis on phase comparators
                                                                               G2p0WR         (b3) = 0
                                                                               G2p0RD         (b2) = 0
                                                                               G2p1WR         (b1) = 0	  TACH - must be 0
                                                                               G2p1OUT        (b0) = 0 */
                                                                               

//#define DEFAULT_AFE_REG_MISC1				0x01						
																			/*!< MISC1 b7:b0
                                                                               CSAvgComp      (b7) = 0		Samples average motor current using external RC
                                                                               REG5VSHORT/SCCL(b6) = 0		5V Short (AUXOCEn=0) or SCCL trip (AUXOCEn=1). Read to clear.
                                                                               OT Fault/SOC   (b5) = 0     	OT Fault (AUXOCEn=0) or SOC trip (AUXOCEn=1). Read to clear.
                                                                               HOC            (b4) = 0     	Hardware over-current status. Read to clear.
                                                                               G1p3RD         (b3) = 0   	
                                                                               CURLIM1        (b2) = 0		Leading edge blanking interval (00b: 800ns, 01b: 400ns,
                                                                               CURLIM0        (b1) = 0		10b: 200ns, 11b: 0ns)
                                                                               VFRAM 1p8      (b0) = 1 		if VDD1p9En clear, Vfram=1.57v (if clear), Vfram=1.8V (if set) */

//#define DEFAULT_AFE_REG_MISC2				0x10						
																			/*!< MISC2 b7:b0
                                                                               FLYBCKENBL     (b7) = 0		
                                                                               ClampEnbl      (b6) = 0
                                                                               ISNSHiGain     (b5) = 0   	Enables hi-gain (10V/V) CS amp. Normal gain (4V/V)
                                                                               MstrEnbl       (b4) = 1     	When clear, powers down circuit blocks to reduce power
                                                                               PWMDLY[1]      (b3) = 0   	Phase comparator sample delay: (00b: 0, 01b: 4us, 
                                                                               PWMDLY[0]      (b2) = 0		10b: 8us, 11b: 14us)
                                                                               PWMON          (b1) = 0	 	When set, PWM comparators sampled during PWM on state
                                                                               Test Lock      (b0) = 0 		Set to 1 for test mode */
#define DEFAULT_AFE_REG_MISC3				0x18						/*!< MISC3 b7:b0
                                                                               G2p3OUT        (b7) = 0
                                                                               G2p3WR         (b6) = 0
                                                                               SnsMode1       (b5) = 0     SnsMode[1:0] = 00b (Digital Hall Sensor mode)
                                                                               PD DIS         (b4) = 1     Disable pull downs on PWM 6:1, SCLK, SIMO and SOMI
                                                                               INERLCKDIS     (b3) = 1     Interlock disable - needs to be set in 1p3 to work
                                                                               SnsMode0       (b2) = 0
                                                                               G2p2OUT        (b1) = 0
                                                                               G2p2WR         (b0) = 0 */

//#define DEFAULT_AFE_REG_MISC4				0x28						
																			/*< MISC4 b7:b0
                                                                              REG5VIN        (b7) = 0		When set, INT generated on 5V short
                                                                              CSBUF          (b6) = 0		When set, motor current averaging enabled
                                                                              VDD1p9EN       (b5) = 1     	When set, VDD=1.9V and VFRAM disabled. Clear: VDD=1.57V
                                                                              AUXOCEN        (b4) = 0     	When set, aux OC enabled (SCCL, SOC). When clear, HOC set by 8b DAC.
                                                                              StayInTest     (b3) = 1     	Set to keep device in test mode. Must be written right after Test Lock
                                                                              AUXOCSEL       (b2) = 0		When set, SCCL = 95% of SOC. When clear, SCCL=90% of SOC [all if AUXOCEN=1]
                                                                              OTDsbl         (b1) = 0 		When set, disables interrupts on any OC. When clear, interrupt on OT
                                                                              CSAVGIN        (b0) = 0 		When set, interrupt when average motor current comparator */




   
#endif /*AFE_DATA_APPLICATION_H_*/
